Thin film transistor with channel protection film of specific resistivity

US8994020B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8994020-B2
Application numberUS-201313799565-A
CountryUS
Kind codeB2
Filing dateMar 13, 2013
Priority dateSep 26, 2012
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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According to one embodiment, a display device includes a thin film transistor. The thin film transistor includes a gate insulating film, a semiconductor layer, a gate electrode, first and second channel protection films, first and second conductive layers, and a passivation film. The semiconductor layer is provided on a major surface of the gate insulating film. The semiconductor layer includes first to seventh portions. The gate insulating film is disposed between the semiconductor layer and the gate electrode. The first channel protection film covers the third portion. The second channel protection film covers the fifth and fourth portions, and an upper surface of the first channel protection film. The first conductive layer covers the sixth portion. The second conductive layer covers the seventh portion. The passivation film covers the first and second portions, the first and second conductive layers, and the second channel protection film.

First claim

Opening claim text (preview).

What is claimed is: 1. A display device comprising a thin film transistor, the thin film transistor comprising: a gate insulating film having a major surface; a semiconductor layer on a portion of the major surface, the semiconductor layer comprising a first portion, a second portion separated from the first portion in a plane parallel to the major surface, a third portion between the first portion and the second portion, a fourth portion between the first portion and the…

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What does patent US8994020B2 cover?
According to one embodiment, a display device includes a thin film transistor. The thin film transistor includes a gate insulating film, a semiconductor layer, a gate electrode, first and second channel protection films, first and second conductive layers, and a passivation film. The semiconductor layer is provided on a major surface of the gate insulating film. The semiconductor layer includes…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).