Solid-state imaging device with plural CCD registers

US8993950B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8993950-B2
Application numberUS-201313781582-A
CountryUS
Kind codeB2
Filing dateFeb 28, 2013
Priority dateAug 29, 2012
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

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In an embodiment, each of first and second pixel rows has pixels. A first transfer gate is arranged between the first and second pixel rows. Second transfer gates are arranged adjacently to odd-numbered pixels of the second pixel row, respectively. Third transfer gates are arranged adjacently to even-numbered pixels of the second pixel row, respectively. A first CCD register is arranged adjacently to the second transfer gates and third transfer gates. Fourth transfer gates are arranged adjacently to odd-numbered accumulation gates of the first CCD register. A second CCD register is arranged adjacently to the fourth transfer gates. An output portion converts transferred charges into a voltage signal. A clear gate controls draining of the charges accumulated in the first pixel row to a first drain portion. A switch gate controls draining of charges transferred in a row direction in the second CCD register to a second drain portion.

First claim

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What is claimed is: 1. A solid-state imaging device, comprising: a first pixel row including pixels which convert incident light photoelectrically and accumulate acquired charges; a second pixel row including pixels which convert incident light photoelectrically and accumulate acquired charges; a first transfer gate arranged between the first pixel row and the second pixel row; second transfer gates arranged adjacently to odd-numbered ones of the pixels of the second pixel r…

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What does patent US8993950B2 cover?
In an embodiment, each of first and second pixel rows has pixels. A first transfer gate is arranged between the first and second pixel rows. Second transfer gates are arranged adjacently to odd-numbered pixels of the second pixel row, respectively. Third transfer gates are arranged adjacently to even-numbered pixels of the second pixel row, respectively. A first CCD register is arranged adjacen…
Who is the assignee on this patent?
Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H04N25/713. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).