Interconnect layer and method for manufacturing the same
US-2024420994-A1 · Dec 19, 2024 · US
US8993439B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993439-B2 |
| Application number | US-201414285969-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 23, 2014 |
| Priority date | Jun 19, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: forming a molding layer on a substrate; sequentially forming a first damascene mask layer and a first mask layer on the molding layer; forming a first mask layer pattern by etching the first mask layer; forming a first damascene pattern by partially etching the first damascene mask layer using the first mask layer pattern as a mask; forming a second damascene mask layer on the f…
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