Semiconductor packages and methods for fabricating the same
US-2024203855-A1 · Jun 20, 2024 · US
Method for fabricating semiconductor device that includes forming passivation film along side wall of via hole
US8993436B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993436-B2 |
| Application number | US-201414199031-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 6, 2014 |
| Priority date | Apr 10, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for fabricating a semiconductor device, the method comprising: sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern; forming a conductive mask pattern including a first opening on the insulating film; forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film; removing the conductive mask pattern; and forming a passiva…
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/087Primary
Electricity · mapped topic
- H10W20/076Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993436B2 cover?
- A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the condu…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/087. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).