Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
Manufacturing method for forming a self aligned contact
US8993433B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993433-B2 |
| Application number | US-201313902977-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 27, 2013 |
| Priority date | May 27, 2013 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.
First claim
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What is claimed is: 1. A manufacturing method of a semiconductor device, at least comprising the following steps: providing a substrate, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate; forming at least one first trench in the first dielectric layer, exposing parts of the S/D region, wherein the manufacturing me…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W20/089Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993433B2 cover?
- The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trenc…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H10W20/089. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).