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Manufacturing method of semiconductor device and semiconductor device
US8993430B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993430-B2 |
| Application number | US-201213411925-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 5, 2012 |
| Priority date | Sep 30, 2011 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern is formed along an inner periphery of the opening of the second core pattern, the first core pattern and the second core pattern are removed, and the process target film is processed to transfer the sidewall pattern and the sidewall dummy pattern.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor device comprising: a plurality of wires formed in a wiring portion on a semiconductor substrate to be parallel to each other at substantially a constant pitch; a plurality of leading lines that are led out from the wires, respectively, and are formed in parallel with each other in a leading portion on the semiconductor substrate at a pitch larger than the wires; dummy leading lines that are formed in the leading portion on the semiconduct…
Assignees
Inventors
Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10W42/00Primary
Electricity · mapped topic
- H10W20/0698Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993430B2 cover?
- According to one embodiment, a first core pattern is formed in a wiring portion on a process target film and a second core pattern, which is led out from the first core pattern and includes an opening, is formed in a leading portion on the process target film, a sidewall pattern is formed along an outer periphery of the first core pattern and the second core pattern and a sidewall dummy pattern…
- Who is the assignee on this patent?
- Matsuda Yuya, Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10W42/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).