Structure and method to create a damascene local interconnect during metal gate deposition

Patent metadata

Field	Value
Publication number	US-8993428-B2
Application number	US-57318809-A
Country	US
Kind code	B2
Filing date	Oct 5, 2009
Priority date	Oct 5, 2009
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

A method and structure to create damascene local interconnect during metal gate deposition. A method includes: forming a gate dielectric on an upper surface of a substrate; forming a mandrel on the gate dielectric; forming an interlevel dielectric (ILD) layer on a same level as the mandrel; forming a trench in the ILD layer; removing the mandrel; and forming a metal layer on the gate dielectric and in the trench.

First claim

What is claimed:

1. A method of forming a semiconductor structure, comprising:
forming a gate dielectric on an upper surface of a substrate;
forming a mandrel on the gate dielectric;
forming an interlevel dielectric (ILD) layer on a same level as the mandrel;
forming a barrier layer between the substrate and the ILD layer;
forming a trench in the ILD layer;
removing the mandrel; and
forming a metal layer on the gate dielectric, which also fills the trench, to substanti…

Assignees

• Ellis-Monaghan John J
• Gambino Jeffrey P
• Peterson Kirk D
• Rankin Jed H
• Robison Robert R
• IBM

Inventors

• Ellis-Monaghan John J
• Gambino Jeffrey P
• Peterson Kirk D
• Rankin Jed H
• Robison Robert R

Classifications

• H10W20/089

  Electricity · mapped topic

• H10W20/0698 Primary

  Electricity · mapped topic

• H10D86/451

  Electricity · mapped topic

• H10D86/60

  Electricity · mapped topic

• H10D64/691

  Electricity · mapped topic