High-voltage transistor architectures, processes of forming same, and systems containing same

Patent metadata

Field	Value
Publication number	US-8993401-B2
Application number	US-201313927694-A
Country	US
Kind code	B2
Filing date	Jun 26, 2013
Priority date	Aug 18, 2010
Publication date	Mar 31, 2015
Grant date	Mar 31, 2015

Abstract

An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD0) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.

First claim

What is claimed is:

1. A process of forming a transistor, comprising:
forming a gate upon a semiconductive substrate above a channel;
forming an interlayer dielectric layer (ILD0) above and on the semiconductive substrate;
opening a source via in the ILD0 to expose a source implant in the channel;
opening a drain via in the ILD0 to expose a drain implant in a drain well in the semiconductive substrate, wherein the drain well forms a junction with the channel;
saliciding a…

Assignees

• Intel Corp

Inventors

• Hafez Walid M
• Jan Chia-Hong
• Rahman Anisur

Classifications

• H10D84/856

  Electricity · mapped topic

• H10D64/665

  Electricity · mapped topic

• H10D84/83

  Electricity · mapped topic

• H10D84/038

  Electricity · mapped topic

• H10D84/013 Primary

  Electricity · mapped topic