Pillar structure for memory device and method

US8993397B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8993397-B2
Application numberUS-201314011577-A
CountryUS
Kind codeB2
Filing dateAug 27, 2013
Priority dateJun 11, 2010
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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Abstract

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A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.

First claim

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What is claimed is: 1. A method of forming a semiconductor device having a memory device, comprising: providing a semiconductor substrate having a surface region; forming a first dielectric layer overlying the surface region of the semiconductor substrate; forming a first via within the first dielectric layer material; depositing a liner material within the first via; depositing a metal-containing material over and in contact with the liner material and filling the first v…

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What does patent US8993397B2 cover?
A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed…
Who is the assignee on this patent?
Crossbar Inc
What technology area does this patent fall under?
Primary CPC classification H01L45/1675. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).