Semiconductor device and fabrication method thereof

US8993384B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8993384-B2
Application numberUS-201313913511-A
CountryUS
Kind codeB2
Filing dateJun 9, 2013
Priority dateJun 9, 2013
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A fabrication method for a semiconductor device, comprising: forming a fin structure, protruding from a surface of a substrate, wherein the fin structure comprises a top surface and two side surfaces; forming an isolation structure to surround the fin structure; forming a gate structure, overlaying the top surface and the two side surfaces of a portion of the fin structure, and covering a portion of the isolation structure; after the step of forming th…

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What does patent US8993384B2 cover?
A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a port…
Who is the assignee on this patent?
United Microelectronics Corp
What technology area does this patent fall under?
Primary CPC classification H10D30/6211. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).