Flip-chip BGA assembly process

US8993378B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8993378-B2
Application numberUS-201113225614-A
CountryUS
Kind codeB2
Filing dateSep 6, 2011
Priority dateSep 6, 2011
Publication dateMar 31, 2015
Grant dateMar 31, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method for assembling a flip chip ball grid array package includes mounting solder spheres to a ball grid array substrate, applying flux to a plurality of flip chip solder bumps provided on a diced wafer, aligning the ball grid array substrate over a chip on the diced wafer, picking and separating the chip from the diced wafer by urging the chip upwards towards the ball grid array substrate until the flip chip solder bumps on the chip come in contact with the ball grid array substrate, whereby the chip attaches to the ball grid array substrate in an upside-down orientation, and subjecting the chip and the ball grid array substrate to a thermal process whereby the solder spheres reflow and form solder balls and the flip chip solder bumps reflow and form solder joints between the chip and the ball grid array.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for assembling a flip chip ball grid array package, wherein the ball grid array package comprising a chip joined to a ball grid array substrate, the ball grid array substrate comprising a first side and a second side, the method comprising: picking the chip from a diced wafer by urging the chip upwards towards the ball grid array substrate, while the ball grid array substrate is being held over the chip, until the chip separates from the diced wafer…

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What does patent US8993378B2 cover?
A method for assembling a flip chip ball grid array package includes mounting solder spheres to a ball grid array substrate, applying flux to a plurality of flip chip solder bumps provided on a diced wafer, aligning the ball grid array substrate over a chip on the diced wafer, picking and separating the chip from the diced wafer by urging the chip upwards towards the ball grid array substrate u…
Who is the assignee on this patent?
Liu Yu-Chih, Lu Jing Ruei, Lin Wei-Ting, and 3 more
What technology area does this patent fall under?
Primary CPC classification H10W95/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).