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Evaluation pattern, method for manufacturing semiconductor device, and semiconductor wafer
US8993354B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993354-B2 |
| Application number | US-201313841087-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 15, 2013 |
| Priority date | Sep 14, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
Official abstract text for this publication.
According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes heating a resistor pattern by scanning the resistor pattern with a first beam. The resistor pattern includes resistors, and a connection structure connecting the resistors in series. The resistors is arranged in matrix of two or more rows and two or more columns. The method includes further heating the resistor pattern by scanning the resistor pattern with a second beam having a different scan direction as that of the first beam.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing a semiconductor device in a semiconductor wafer, the semiconductor device comprising a resistor pattern including a plurality of resistors provided in the semiconductor wafer and arranged in matrix of at least two rows and at least two columns, and a connection structure configured to connect the plurality of resistors in series, wherein the plurality of resistors includes a plurality of first resistors provided in a chip of the sem…
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Frequently asked questions
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- What does patent US8993354B2 cover?
- According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes heating a resistor pattern by scanning the resistor pattern with a first beam. The resistor pattern includes resistors, and a connection structure connecting the resistors in series. The resistors is arranged in matrix of two or more rows and two or more columns. The method includes …
- Who is the assignee on this patent?
- Toshiba Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D1/47. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).