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Multilayer ceramic substrate and method for producing the same
US8993105B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8993105-B2 |
| Application number | US-94007310-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2010 |
| Priority date | May 15, 2008 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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When a multilayer ceramic substrate with a cavity is reduced in thickness, a bottom wall portion defining the bottom of the cavity is reduced in thickness, thereby leading to the problem that the bottom wall portion is likely to be broken. A bottom wall portion defining a cavity of a multilayer ceramic substrate has a stack structure formed with a high thermal expansion coefficient layer sandwiched between first and second low thermal expansion coefficient layers. This configuration generates compression stress in the low thermal expansion coefficient layers during a cooling process after firing, thereby allowing the mechanical strength at the bottom wall portion to be improved.
First claim
Opening claim text (preview).
What is claimed is: 1. A multilayer ceramic substrate including a cavity, comprising: a peripheral wall portion including a first ceramic layer including a through hole arranged to define the cavity; and a bottom wall portion including a plurality of second ceramic layers not including a through hole; wherein the plurality of second ceramic layers of the bottom wall portion includes at least two types of ceramic layers, the at least two types of ceramic layers including a firs…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8993105B2 cover?
- When a multilayer ceramic substrate with a cavity is reduced in thickness, a bottom wall portion defining the bottom of the cavity is reduced in thickness, thereby leading to the problem that the bottom wall portion is likely to be broken. A bottom wall portion defining a cavity of a multilayer ceramic substrate has a stack structure formed with a high thermal expansion coefficient layer sandwi…
- Who is the assignee on this patent?
- Iida Yuichi, Murata Manufacturing Co
- What technology area does this patent fall under?
- Primary CPC classification H05K1/183. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).