Victim cache that supports draining write-miss entries
US-2024264952-A1 · Aug 8, 2024 · US
US8990833B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990833-B2 |
| Application number | US-201113330850-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 20, 2011 |
| Priority date | Dec 20, 2011 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Official abstract text for this publication.
A circuit arrangement, method, and program product for communicating data between hardware threads of a network on a chip processing unit utilizes shared inboxes to communicate data to pools of hardware threads. The associated hardware in the pools threads receive data packets from the shared inboxes in response to issuing work requests to an associated shared inbox. Data packets include a source identifier corresponding to a hardware thread from which the data packet was generated, and the shared inboxes may manage data packet distribution to associated hardware threads based on the source identifier of each data packet. A shared inbox may also manage workload distribution and uneven workload lengths by communicating data packets to hardware threads associated with the shared inbox in response to receiving work requests from associated hardware threads.
Opening claim text (preview).
What is claimed is: 1. A method for communicating data in a network on chip (NOC) processing unit that includes a plurality of nodes, each node including a router and an integrated processor block, each integrated processor block including at least one hardware thread, and each hardware thread executing an instance of a stage of a plurality of stages of a software pipeline, wherein the routers of each node are coupled together in an on-chip network, the method comprising: generati…
Physics · mapped topic
Physics · mapped topic
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