Software Operator for Deploying and Managing Bare Metal Clusters
US-2024320022-A1 · Sep 26, 2024 · US
Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core
US8990816B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990816-B2 |
| Application number | US-201213452745-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 20, 2012 |
| Priority date | Jan 6, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
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Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of providing hardware thread-specific information in a multi-threaded processor supporting a number of hardware threads for executing processes within multiple logical partitions, the method comprising: maintaining the hardware thread specific information in a register within the multi-threaded processor; detecting access to the hardware thread-specific information by a currently-executing one of the processes; determining whether or not a privi…
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Physics · mapped topic
- G06F9/45541Primary
Physics · mapped topic
- G06F9/45558Primary
Physics · mapped topic
Physics · mapped topic
- G06F21/6218Primary
Physics · mapped topic
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Frequently asked questions
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- What does patent US8990816B2 cover?
- Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is trans…
- Who is the assignee on this patent?
- Frazier Giles R, Mealy Bruce, Nayar Naresh, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification G06F9/45541. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).