Cell-aware fault model generation for delay faults

Patent metadata

Field	Value
Publication number	US-8990760-B2
Application number	US-201113219564-A
Country	US
Kind code	B2
Filing date	Aug 26, 2011
Priority date	Aug 26, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

Cell-aware fault models for delay faults are created for library cells. Analog one-clock-cycle fault simulations are first performed on a transistor-level netlist of a cell to identify type one detectable defects and type two detectable defects in defects of interest. The type one detectable defects are detectable by one-clock-cycle testing and their fault models may be created based on results of the analog one-clock-cycle fault simulations. The type two detectable defects are defects for which two-cycle detection conditions may be calculated from corresponding results of the analog one-cycle fault simulations. Analog two-clock-cycle fault simulations are then performed for the rest defects in the defects of interest to determine type three detectable defects and their detection conditions. The created cell-aware fault models may be used to generate cell-aware test patterns.

First claim

What is claimed is:

1. A method of cell-aware fault model generation, executed by at least one processor of a computer, comprising:
receiving a transistor-level netlist and defects of interest for a cell;
performing, at least one processor of a computer, analog one-cycle fault simulations based on the transistor-level netlist to identify type one detectable defects and type two detectable defects in the defects of interest;
determining calculated two-cycle detection conditions…

Assignees

• Hapke Friedrich
• Redemund Wilfried
• Schloeffel Juergen
• Glowatz Andreas
• Mentor Graphics Corp

Inventors

• Hapke Friedrich
• Redemund Wilfried
• Schloeffel Juergen
• Glowatz Andreas

Classifications

• G06F30/367

  Physics · mapped topic

• G01R31/31835 Primary

  Physics · mapped topic

• G06F17/5036

  Physics · mapped topic