Numerical area recovery

Patent metadata

Field	Value
Publication number	US-8990750-B2
Application number	US-201313954927-A
Country	US
Kind code	B2
Filing date	Jul 30, 2013
Priority date	Jul 30, 2013
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

Systems and techniques are described for performing area recovery on a circuit design. Some embodiments can select a gate for area recovery in accordance with a reverse-levelized processing order, wherein an output pin of a driver gate is electrically coupled to an input pin of the gate. Next, the embodiment can determine a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design. The embodiment can then downsize the gate based on the maximum delay value, wherein said downsizing comprises inputting the maximum delay value in a closed-form expression. Timing margin computation can be used to ensure that timing violations are not worsened when the embodiment recovers area from non-timing-critical regions of the circuit design.

First claim

What is claimed is:

1. A method for performing area recovery on a circuit design, the method comprising:
selecting a gate for area recovery, wherein an output of a driver gate is electrically coupled to an input of the gate;
determining a maximum delay value from an input pin of the driver gate to an output pin of the gate that does not create new timing requirement violations or worsen existing timing requirement violations at any of the timing endpoints of the circuit design;…

Assignees

• Synopsys Inc

Inventors

• Iyer Mahesh A
• Mottaez Amir H

Classifications

• G06F30/327 Primary

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic