Evaluation of thermal instability stress testing
US-2015369855-A1 · Dec 24, 2015 · US
Method and apparatus for optimizing memory-built-in-self test
US8990749B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990749-B2 |
| Application number | US-201213625733-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 24, 2012 |
| Priority date | Sep 24, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
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Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption and timing. The cost functions are minimized using optimization techniques, resulting in an optimized grouping of memory devices and an optimized schedule for MBIST testing. The estimated parameters may be derived from a compact model constructed from data experimentally-derived from various memory devices. This approach allows a circuit designer to generate and revise groupings and schedules prior to running a full design flow, saving time and cost, while still achieving high-quality results.
First claim
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We claim: 1. A computer-implemented method of scheduling memory built-in-self-test (MBIST) for an integrated circuit having a plurality of memory devices, comprising: (a) assigning a weight to each scheduling parameter of a plurality of scheduling parameters associated with MBIST circuitry of the integrated circuit, wherein the MBIST circuitry is to be fabricated on an integrated circuit substrate together with an integrated circuit design having a plurality of memory devices to b…
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- G06F30/333Primary
Physics · mapped topic
- G06F30/327Primary
Physics · mapped topic
Physics · mapped topic
- G06F17/505Primary
Physics · mapped topic
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- What does patent US8990749B2 cover?
- Testing of memories is done using an optimized memory built-in-self-test (MBIST) approach, including the generation of compact models for memory. Cost functions are constructed from estimated parameters affecting MBIST, and a user is able to assign relative weights to the parameters. Estimated parameters include MBIST area, wiring congestion, and timing overhead, as well as power consumption an…
- Who is the assignee on this patent?
- Arora Puneet, Kaushik Navneet, Gregor Steven, and 2 more
- What technology area does this patent fall under?
- Primary CPC classification G06F30/333. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).