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Logical Verification Apparatus and Method
US8990747B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990747-B2 |
| Application number | US-201414244483-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 3, 2014 |
| Priority date | Apr 5, 2013 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
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A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a verification subject circuit based on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined based on the connection relationships being derived. Related I/Fs, which are related to inputs to the logics and are interfaces to an outside of the verification subject circuit, are extracted based on the connection information. Second priority for verifying the related I/Fs is determined based on the first priority.
First claim
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What is claimed is: 1. A logical verification apparatus, comprising: a processor; and a storage part configured to store description data which describe an operation of a verification subject circuit, a display part configured to display a result from verifying the verification subject circuit by using a logical simulation by the processor, wherein the processor performs a logical verification process including: deriving connection relationships pertinent to an input/output…
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- G06F30/3323Primary
Physics · mapped topic
- G06F17/504Primary
Physics · mapped topic
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- What does patent US8990747B2 cover?
- A verification item extraction apparatus is disclosed that performs a priority determination process. Connection relationships pertinent to input/output are derived for each of logics in a verification subject circuit based on connection information acquired from description data in a storage part. A first priority for verifying the logics is determined based on the connection relationships bei…
- Who is the assignee on this patent?
- Fujitsu Semiconductor Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F30/3323. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).