Tracing support for interconnect fabric

Patent metadata

Field	Value
Publication number	US-8990633-B2
Application number	US-42764609-A
Country	US
Kind code	B2
Filing date	Apr 21, 2009
Priority date	Apr 21, 2009
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

Complex on-chip interconnect fabrics, particularly those that include point-to-point interconnects and coherent routing networks, can present significant challenges for conventional trace techniques that may be applied in an effort to efficiently provide an external debugger with visibility into on-chip interconnect transactions. Embodiments described herein generate and supply separate in-circuit-trace messages including address messages and data messages, which are sent out (i.e., off-chip) to external debug tools generally without delay and coincident with the distinct, but related, trace events within address and data paths of the interconnect fabric. These separate message instances embed appropriate tag and mark values to allow the message instances to be post-processed and correlated by the external debug tools so as to reconstruct the transaction information for operations performed in the on-chip interconnect.

First claim

What is claimed is:

1. A method of testing an integrated circuit chip, the method comprising:
based on operations performed within an interconnect fabric located on-chip, receiving off-chip at least two separate streams of trace messages, the first stream including trace messages corresponding to a first transaction phase of respective ones of the operations and the second stream including trace messages corresponding to a second transaction phase of the respective operations; and…

Assignees

• Xu Zheng
• Deshpande Sanjay
• Snyder Michael
• Freescale Semiconductor Inc

Inventors

• Xu Zheng
• Deshpande Sanjay
• Snyder Michael

Classifications

• G06F11/26 Primary

  Physics · mapped topic