Method and apparatus to use DRAM as a cache for slow byte-addressible memory for efficient cloud applications
US-12174739-B2 · Dec 24, 2024 · US
US8990541B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990541-B2 |
| Application number | US-201213611204-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 12, 2012 |
| Priority date | Sep 12, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A method, system, and computer program product for improving memory utilization of sparse pages are provided in the illustrative embodiments. A set of virtual pages is identified. Each virtual page in the set of virtual pages is a sparse virtual page. The set of virtual pages includes a first sparse virtual page and a second sparse virtual page. At least a portion of data of the first sparse virtual page in the set of virtual pages is stored in a first physical page. The first physical page belongs to a set of consolidation physical pages, and the first physical page also stores at least a portion of the data of the second sparse virtual page. The first and the second sparse pages are mapped to the first physical page.
Opening claim text (preview).
What is claimed is: 1. A data processing system for improving memory utilization of sparse pages, the data processing system comprising: a storage device including a storage medium, wherein the storage device stores computer usable program code; and a processor, wherein the processor executes the computer usable program code, and wherein the computer usable program code comprises: computer usable code for identifying, using a processor, a set of virtual pages, wherein each vir…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Related publications grouped by family.
Free tools are coming soon. Tell us what you want to track and we'll notify you.
Answers are generated from the same data shown on this page.