Digital signal processing data transfer

Patent metadata

Field	Value
Publication number	US-8990522-B2
Application number	US-201213646649-A
Country	US
Kind code	B2
Filing date	Oct 5, 2012
Priority date	Oct 26, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

First claim

We claim:

1. A digital signal processing system, comprising:
a memory device;
a memory access controller providing a plurality of channels for accessing the memory device;
a plurality of fixed function accelerators, each arranged to perform a specialised signal processing task, each connected to the memory access controller and each configured to read data from the memory device via one of the channels, perform one or more operations on the data, and write data to the memory d…

Assignees

• Imagination Tech Ltd

Inventors

• Anderson Adrian J
• Wass Gary C
• Davies Gareth J

Classifications

• G06F9/542 Primary

  Physics · mapped topic

• G06F9/3851 Primary

  Physics · mapped topic

• G06F9/544

  Physics · mapped topic

• G06F13/28 Primary

  Physics · mapped topic

• G06F13/385

  Physics · mapped topic