Replacing cache lines in a cache memory based at least in part on cache coherency state information

US8990506B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8990506-B2
Application numberUS-63919109-A
CountryUS
Kind codeB2
Filing dateDec 16, 2009
Priority dateDec 16, 2009
Publication dateMar 24, 2015
Grant dateMar 24, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. A processor comprising: a cache memory comprising an adaptive shared cache memory comprising a plurality of banks each to be associated with a corresponding core and to provide private cache storage and shared cache storage, the cache memory including a plurality of cache lines each having a data field to store data and a tag field including a state portion to store a cache coherency state of the corresponding data and a weight portion to store a weight corr…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US8990506B2 cover?
In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of…
Who is the assignee on this patent?
Cherukuri Naveen, Brzezinski Dennis W, Schoinas Ioannis T, and 4 more
What technology area does this patent fall under?
Primary CPC classification G06F12/121. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).