Address Range Based Memory Hints for Prefetcher, Cache and Memory Controller
US-2024385966-A1 · Nov 21, 2024 · US
US8990504B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990504-B2 |
| Application number | US-201113180380-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 11, 2011 |
| Priority date | Jul 11, 2011 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.
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What is claimed is: 1. A cache page management method, comprising: paging a memory page from a real memory to a virtual memory, the virtual memory being a peripheral device to a computer system that includes the real memory and an input/output controller; paging out the memory page from the virtual memory to the input/output controller; paging the memory page from the input/output controller into the real memory; modifying the memory page in the real memory to an updated mem…
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