Memory management unit that applies rules based on privilege identifier
US-9465753-B2 · Oct 11, 2016 · US
Arbiter for asynchronous state machines
US8990466B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8990466-B2 |
| Application number | US-201213482753-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 29, 2012 |
| Priority date | May 29, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
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An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.
First claim
Opening claim text (preview).
What is claimed is: 1. An arbiter for processing a plurality of asynchronous data signals, wherein each data signal is associated with a respective request signal and a respective acknowledge signal, the arbiter comprising: a latch array comprising a plurality of individual latches, an input coupled to receive the data signals and request signals as input signals, and an output coupled to provide a data vector and a validity vector as output signals, the data vector including valu…
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Electricity · mapped topic
- G06F13/366Primary
Physics · mapped topic
Physics · mapped topic
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- What does patent US8990466B2 cover?
- An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the dat…
- Who is the assignee on this patent?
- Bacigalupo Tommaso, Infineon Technologies Austria
- What technology area does this patent fall under?
- Primary CPC classification G06F13/366. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).