CPU interconnect device

Patent metadata

Field	Value
Publication number	US-8990460-B2
Application number	US-201213707209-A
Country	US
Kind code	B2
Filing date	Dec 6, 2012
Priority date	Jun 27, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

The present disclosure provides a CPU interconnect device, the CPU interconnect device connects with a first CPU, which includes a quick path interconnect QPI interface and a serial deserial SerDes interface, the quick path interconnect QPI interface receives serial QPI data sent from a CPU, converts the received serial QPI data into a parallel QPI data, and outputs the parallel QPI data to the serial deserial SerDes interface; the serial deserial SerDes interface converts the parallel QPI data output by the QPI interface into a high-speed serial SerDes data and then send the high-speed serial SerDes data to another CPU interconnect device connected with another CPU. The defects of poor scalability, long data transmission delay, and a high cost of an existing interconnect system among CPUs can be solved.

First claim

What is claimed is:

1. A CPU interconnect device that is configured to connect to a CPU, the CPU interconnect device comprising:
a quick path interconnect (QPI) interface; and
a serial deserial (SerDes) interface,
wherein:
the QPI interface is configured to receive first serial QPI data from the CPU, convert the received first serial QPI data into first parallel QPI data, and output the first parallel QPI data to the SerDes interface; and
the SerDes interface is configured…

Assignees

• Huawei Tech Co Ltd

Inventors

• Chang Sheng
• Yang Rongyu
• Hou Xinyu

Classifications

• G06F15/17 Primary

  Physics · mapped topic

• G06F13/4265

  Physics · mapped topic

• G06F13/4059

  Physics · mapped topic

• G06F13/4282

  Physics · mapped topic

• G06F2213/0038

  Physics · mapped topic