Method for handling access transactions and related system

Patent metadata

Field	Value
Publication number	US-8990436-B2
Application number	US-201313904379-A
Country	US
Kind code	B2
Filing date	May 29, 2013
Priority date	May 30, 2012
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.

First claim

The invention claimed is:

1. An apparatus comprising:
a processor configured to generate a plurality of transactions;
a plurality of target circuits each having an address; and
a logic circuit coupled between said processor and said plurality of target circuits;
said logic circuit comprising
an identifying circuit configured to generate an identifier for each transaction based upon at least one address associated with each transaction, wherein not all transactions have the…

Assignees

• St Microelectronics Srl

Inventors

• Mangano Daniele
• Pisasale Salvatore
• Dondini Mirko

Classifications

• G06F13/1626 Primary

  Physics · mapped topic

• G06F2213/0038

  Physics · mapped topic

• G06F9/466 Primary

  Physics · mapped topic