Method and circuit of clock and data recovery with built in jitter tolerance test

Patent metadata

Field	Value
Publication number	US-8989246-B2
Application number	US-201314041828-A
Country	US
Kind code	B2
Filing date	Sep 30, 2013
Priority date	Feb 18, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes.

First claim

What is claimed is:

1. A clock and data recovery circuit, comprising:
a sampler for sampling an input data according to a recovery clock to generate a sampling value;
a phase detector for detecting a phase difference between the recovery clock and the input data to generate a first voltage signal and a second voltage signal;
a charge pump for converting the first voltage signal and the second voltage signal into a phase-difference current signal;
a jitter source for generati…

Assignees

• Realtek Semiconductor Corp

Inventors

• Wu Pei-Si

Classifications

• H04L1/205 Primary

  Electricity · mapped topic

• H03L7/0807 Primary

  Electricity · mapped topic

• H03L7/0814

  Electricity · mapped topic

• H03L7/093

  Electricity · mapped topic