Neural network computation circuit, control circuit therefor, and control method therefor
US-2024411520-A1 · Dec 12, 2024 · US
US8988935B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8988935-B2 |
| Application number | US-201213720232-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 19, 2012 |
| Priority date | Dec 22, 2011 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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The present disclosure concerns a method for writing to a self-referenced MRAM cell comprising a magnetic tunnel junction comprising: a storage layer including a first ferromagnetic layer having a first storage magnetization, a second ferromagnetic layer having a second storage magnetization, and a non-magnetic coupling layer separating the first and second ferromagnetic layers; a sense layer having a free sense magnetization; and a tunnel barrier layer included between the sense and storage layers; the first and second ferromagnetic layers being arranged such that a dipolar coupling between the storage) and the sense layers is substantially null; the method comprising: switching the second ferromagnetic magnetization by passing a spin-polarized current in the magnetic tunnel junction; wherein the spin-polarized current is polarized when passing in the sense layer, in accordance with the direction of the sense magnetization. The MRAM cell can be written with low power consumption.
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The invention claimed is: 1. Method for writing to a self-referenced MRAM cell comprising a magnetic tunnel junction comprising: a storage layer including a first ferromagnetic layer having a first storage magnetization, a second ferromagnetic layer having a second storage magnetization, and a non-magnetic coupling layer separating the first and second ferromagnetic layers; a sense layer having a free sense magnetization; and a tunnel barrier layer included between the sense a…
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