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Nonvolatile memory device and related operating method
US8988929B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8988929-B2 |
| Application number | US-201314093076-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 29, 2013 |
| Priority date | Dec 26, 2012 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
Official abstract text for this publication.
A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping voltage of the clamping circuit and a resistance of the line resistor according to a relative location of the selected one of the resistance memory cells within the memory cell array, and applying a read current to the sense node and sensing a voltage of the sense node to read a data stored in the selected one of the resistance memory cells.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for driving a nonvolatile memory device, comprising: determining a read voltage of a nonvolatile memory cell, the read voltage being determined such that a resultant sensing margin is equal to or higher than a predetermined level; and adjusting at least one of clamping voltage and a line resistor connected to the nonvolatile memory cell so that the determined read voltage is applied to the nonvolatile memory cell when reading a data stored in the…
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Physics · mapped topic
Physics · mapped topic
- G11C13/004Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US8988929B2 cover?
- A method is for driving a nonvolatile memory device, where the nonvolatile memory device includes a memory cell array composed of resistance memory cells. The method includes electrically connecting a clamping circuit, a line resistor and a selected one of the resistance memory cells in series between a sensing node and a ground. The method further includes adjusting at least one of a clamping …
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification G11C13/004. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).