Nonvolatile semiconductor memory device in which polarities of voltages in forming operation and set operation are different from each other

US8988925B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8988925-B2
Application numberUS-201213597318-A
CountryUS
Kind codeB2
Filing dateAug 29, 2012
Priority dateMar 2, 2010
Publication dateMar 24, 2015
Grant dateMar 24, 2015

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Abstract

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A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

First claim

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What is claimed is: 1. A nonvolatile semiconductor memory device, comprising: a plurality of first lines; a plurality of second lines extending so as to intersect the first lines; a plurality of memory cells disposed at intersections of the first lines and the second lines, each of the memory cells including a variable resistor; and a control circuit for controlling a voltage applied to the memory cells, the plurality of memory cells being able to change from a write state…

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What does patent US8988925B2 cover?
A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is c…
Who is the assignee on this patent?
Ichihara Reika, Tsukamoto Takayuki, Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification G11C11/00. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).