Display devices

Patent metadata

Field	Value
Publication number	US-8988645-B2
Application number	US-201213596647-A
Country	US
Kind code	B2
Filing date	Aug 28, 2012
Priority date	Sep 1, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A display device includes a panel including pixels defined by data lines and gate lines, a housing chassis covering a sidewall and an edge of the panel, a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal, a chip on film connecting the printed circuit board to the panel, the chip on film between the housing chassis and the sidewall of the panel, a driver integrated circuit mounted on the chip on film and configured to respond to the control signal and drive at least one of the data signal and the gate signal applied to the data lines and the gate lines, and a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis.

First claim

What is claimed is:

1. A display device comprising:
a panel including pixels defined by data lines and gate lines;
a housing chassis covering a sidewall and an edge of the panel;
a printed circuit board under the panel, the printed circuit board including circuit elements configured to generate at least one of a data signal, a gate signal, and a control signal applied to at least one of the data lines and the gate lines;
a chip on film connecting the printed circuit board to the panel, the chip on film being between the housing chassis and the sidewall of the panel;
a driver integrated circuit mounted on the chip on film, the driver integrated circuit being configured to respond to the control signal received from the circuit elements and drive the data signal and the gate signal applied to the data lines and the gate lines; and
a connection unit attaching the chip on film to the housing chassis and dissipating heat generated by the driver integrated circuit to the housing chassis., wherein the connection unit includes at least one magnet located between the chip on film and the panel.

2. The display device of claim 1 , wherein the at least one magnet includes at least one of a bar magnet, a sheet magnet, and a powder magnet.

3. The display device of claim 1 , wherein the at least one magnet affixes the chip on film to the housing chassis.

4. The display device of claim 1 , wherein the at least one magnet is adhered to the chip on film.

5. The display device of claim 4 , wherein the at least one magnet includes at least one of rare earth metals including neodymium (Nd), samarium (Sm), and cobalt (Co).

6. The display device of claim 1 , wherein the chip on film is a tape carrier package.

7. The display device of claim 1 , further comprising:
a mold frame surrounding the sidewall of the panel in the housing chassis.

8. The display device of claim 7 , further comprising:
a backlight unit in the mold frame under the panel and configured to provide light to the panel;
a light guide plate below the panel in the mold frame and configured to input light provided from the backlight unit to the panel;
optical sheets between the light guide plate and the panel; and
a reflection plate below the light guide plate.

9. The display device of claim 8 , further comprising:
a bottom chassis between the printed circuit board and the reflection plate, the bottom chassis supporting the mold frame and the reflection plate and being combined with the housing chassis.

10. The display device of claim 1 , wherein the at least one magnet includes two magnets located on opposite sides of the driver integrated circuit.

11. A display device, comprising:
a mold frame;
a housing chassis enclosing a sidewall and an edge of the mold frame;
a flexible substrate passing between the housing chassis and the sidewall of the mold frame;
an integrated circuit on the flexible substrate, the integrated circuit being configured to drive the display device; and
a connection unit attaching the flexible substrate to the housing chassis and dissipating heat generated by the integrated circuit to the housing chassis, wherein the connection unit includes at least one magnet located between the flexible substrate and the mold frame.

12. The device of claim 11 , wherein the at least one magnet affixes the flexible substrate to the housing chassis using magnetic force.

13. The device of claim 11 , wherein the at least one magnet is adhered to the flexible substrate.

14. The device of claim 11 , wherein the mold frame includes a groove, and the integrated circuit is aligned with the groove.

15. The device of claim 11 , wherein the flexible substrate is a chip on film.

16. The device of claim 15 , wherein the chip on film is a tape carrier package.

17. The device of claim 11 , further comprising:
a display panel in the mold frame;
a backlight unit in the mold frame, the backlight unit configured to provide light to the display panel;
a light guide plate below the display panel, the light guide configured to input light from the backlight unit to the display panel;
an optical sheet between the light guide plate and the panel;
a reflection plate in the mold frame below the light guide plate;
a bottom chassis below the reflection plate, the bottom chassis supporting the mold frame, and the bottom chassis combining with the housing chassis to form the display device; and
a printed circuit board below the bottom chassis, the printed circuit board including circuit elements configured to send a control signal to the integrated circuit.

18. The device of claim 11 , wherein the at least one magnet includes two magnets located on opposite sides of the integrated circuit.

Assignees

• Kim Jichul
• Kim Young-Deuk
• Cho Eunseok
• Choi Mi-Na
• Samsung Electronics Co Ltd

Inventors

• Kim Jichul
• Kim Young-Deuk
• Cho Eunseok
• Choi Mi-Na

Classifications

• G02F1/1335

  Structural association of cells with optical devices, e.g. polarisers or reflectors · CPC title

• G06F13/00 Primary

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G02F1/1333 Primary

  Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title