Successive approximation register (SAR) analog-to-digital converter (ADC) having optimized filter

Patent metadata

Field	Value
Publication number	US-8988263-B2
Application number	US-201213562729-A
Country	US
Kind code	B2
Filing date	Jul 31, 2012
Priority date	Sep 29, 2009
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A system such as a mechanically tuned radio can have a signal path to receive and process an incoming radio frequency (RF) signal and to provide the processed signal to a first analog-to-digital converter (ADC) to convert the processed signal to a digital signal and to digitally demodulate the digital signal to obtain an audio signal, where this first ADC is separate from an auxiliary ADC not part of the signal path.

First claim

What is claimed is:

1. A system comprising:
a variable impedance controllable by a manual tuning mechanism to provide an analog signal; and
an analog-to-digital converter (ADC) coupled to the variable impedance to receive the analog signal, the ADC including:
a comparator to compare the analog signal received at a first input with a feedback signal received at a second input;
a successive approximation register (SAR) coupled to the comparator and having N-bits of resolution,…

Assignees

• Zhan Sanyi
• Cooley Daniel J
• Zhang Ligang
• Silicon Lab Inc

Inventors

• Zhan Sanyi
• Cooley Daniel J
• Zhang Ligang

Classifications

• H03M1/46 Primary

  Electricity · mapped topic

• H03M3/506

  Electricity · mapped topic