Clock generation circuit and voltage generation circuit including the clock generation circuit
US-2024235560-A1 · Jul 11, 2024 · US
US8988262B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8988262-B2 |
| Application number | US-201414191297-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 26, 2014 |
| Priority date | Aug 1, 2013 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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A delay circuit includes a first inverter in which a delay time of rising is larger than a delay time of falling, and a second inverter which is connected in series with the first inverter and in which a delay time of falling is larger than a delay time of rising. Transistors for each of the first and second inverters are connected in series between a power supply terminal and a ground terminal.
Opening claim text (preview).
What is claimed is: 1. A delay circuit comprising: a first inverter in which a delay time of rising is larger than a delay time of falling; and a second inverter which is connected in series with the first inverter, and in which a delay time of falling is larger than a delay time of rising, wherein transistors for each of the first inverter and the second inverter are connected in series between a first power terminal and a second power terminal. 2. The d…
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