Method for operating memory device and apparatuses performing the method

Patent metadata

Field	Value
Publication number	US-8988101-B2
Application number	US-201213617395-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Sep 21, 2011
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

According to example embodiments, a method for operating a memory device includes receiving an on-die termination (ODT) signal through an ODT pin, and issuing a command or controlling an ODT circuit according to the ODT signal.

First claim

What is claimed is:

1. A method for operating a memory device comprising:
receiving an ODT signal through an on-die termination (ODT) pin; and
issuing a command or controlling an ODT circuit according to the ODT signal, wherein
the command is a refresh command, or
the command is a pre-charge all banks command, or
the command is issued when the memory device is powered down.

2. The method of claim 1 , wherein
the ODT circuit includes a termination resistor, and
the controlling the ODT circuit includes one of changing a resistance of the termination resistor of the ODT circuit, turning on the ODT circuit, and turning off the ODT circuit.

3. The method of claim 2 , wherein the resistance of the termination resistor is changed in response to the ODT signal when the level of the ODT signal at every edge of a clock signal is continuously high.

4. The method of claim 1 , wherein the command is issued in response to the ODT signal when the level of the ODT signal at each edge of clock signal is toggling.

5. The method of claim 1 , wherein the command is the refresh command.

6. The method of claim 1 , wherein the command is the precharge all banks command.

7. The method of claim 1 , wherein the command is issued when the memory device is powered down.

8. A memory device comprising:
an on-die termination (ODT) pin configured to receive an ODT signal;
an ODT detector configured to detect the ODT signal;
a command decoder configured to issue a command according to the ODT signal, wherein
the command is a refresh command,
the command is a precharge all banks command, or
the command is issued when the memory device is powered down;
an ODT circuit including a termination resistor and a switch; and
an ODT control circuit configured to at least one of change a termination resistance of the ODT circuit, turn on the ODT circuit, and turn off the ODT circuit according to a level of the ODT signal.

9. The memory device of claim 8 , wherein the ODT detector comprises:
a plurality of latches, and
a ith latch (1<i≦(N−1)) among the plurality of latches detects a level of an output signal of a (i−1)th latch in response to a clock signal.

10. The memory device of claim 8 , wherein the ODT control circuit is configured to change the termination resistance in response to the ODT signal when the level of the ODT signal detected at each edge of a clock signal is continuously high.

11. The memory device of claim 8 , wherein the command decoder is configured to issue the command in response to the ODT signal when the level of the ODT signal at each edge of a clock signal is toggling.

12. The memory device of claim 8 , wherein the command is the refresh command.

13. The memory device of claim 8 , wherein the command is the precharge all banks command.

14. A memory module comprising:
at least one rank including at least one memory device of claim 8 .

15. The memory module of claim 14 , wherein the memory module is a dual in-line memory module (DIMM), a dual in-line package memory, a single in-line pin package (SIPP) memory, a single in-line memory module (SIMM), a dual in-line memory module (DIMM) or a small outline DIMM (SO-DIMM).

16. A memory device comprising:
an ODT detector configured to generate a first and a second group of signals in response to an ODT signal and a clock signal;
an ODT control circuit connected to an ODT circuit,
the ODT control circuit configured to receive the first group of signals and control an operation of the ODT circuit in response to the first group of signals; and

a control logic connected to a memory cell array, the control logic configured to receive the second group of signals and issue a command to the memory cell array in response to the second group of signals.

17. The memory device of claim 16 , wherein the command is a refresh command.

18. The memory device of claim 16 , wherein the command is a precharge all banks command.

19. The memory device of claim 16 , wherein
the ODT controller includes,
a first latch configured to generate a first detection signal in response to detecting a first level of the ODT signal corresponding to a first edge of the clock signal;
a second latch configured to generate a second detection signal in response to detecting a second level of the ODT signal corresponding to a second edge of the clock signal;

a third latch configured to generate a third detection signal in response to detecting a third level of the ODT signal corresponding to a third edge of the clock signal; and
a fourth latch configured to generate a fourth detection signal in response to detecting a fourth level of the ODT signal corresponding to a fourth edge of the clock signal; the ODT controller is configured to generate the first group of signals based on the first and second detection signals; and
the ODT controller is configured to generate the second group of signals based on the first to fourth detection signals.

20. The memory device of claim 16 , further comprising:
an on-die termination (ODT) pin configured to receive the ODT signal and output the ODT signal to the ODT detector.

Assignees

• Song In Dal
• Choi Jung Hwan
• Yang Yun Seok
• Samsung Electronics Co Ltd

Inventors

• Song In Dal
• Choi Jung Hwan
• Yang Yun Seok

Classifications

• H03K19/0005

  Modifications of input or output impedance · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1057 Primary

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title