Semiconductor memory device
US-2024334693-A1 · Oct 3, 2024 · US
US8987802B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8987802-B2 |
| Application number | US-201313781066-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 28, 2013 |
| Priority date | Feb 28, 2013 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.
Opening claim text (preview).
What is claimed is: 1. A memory cell, comprising: a control gate located over a floating gate region and a continuous tunnel dielectric layer located under the floating gate region, wherein: the floating gate region comprises plural discrete doped semiconducting or conducting regions separated by an insulator located over the continuous tunnel dielectric layer; and the discrete doped semiconducting or conducting regions have a cylindrical or a hyperbolic paraboloid shape; and…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Electricity · mapped topic
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