Method for using nanoparticles to make uniform discrete floating gate layer

US8987802B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8987802-B2
Application numberUS-201313781066-A
CountryUS
Kind codeB2
Filing dateFeb 28, 2013
Priority dateFeb 28, 2013
Publication dateMar 24, 2015
Grant dateMar 24, 2015

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Abstract

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A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.

First claim

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What is claimed is: 1. A memory cell, comprising: a control gate located over a floating gate region and a continuous tunnel dielectric layer located under the floating gate region, wherein: the floating gate region comprises plural discrete doped semiconducting or conducting regions separated by an insulator located over the continuous tunnel dielectric layer; and the discrete doped semiconducting or conducting regions have a cylindrical or a hyperbolic paraboloid shape; and…

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What does patent US8987802B2 cover?
A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.
Who is the assignee on this patent?
Sandisk Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10D30/0411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).