Method for fabricating display device
US-2024057378-A1 · Feb 15, 2024 · US
Carbon nanotube transistor employing embedded electrodes
US8987705B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8987705-B2 |
| Application number | US-201414150954-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jan 9, 2014 |
| Priority date | Oct 21, 2011 |
| Publication date | Mar 24, 2015 |
| Grant date | Mar 24, 2015 |
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Abstract
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Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of the gate dielectric along the direction of an alternating current (AC) electrical field generated by applying a voltage between the two embedded electrodes. A source contact electrode and a drain contact electrode are formed by depositing a conductive material on both ends of the carbon nanotubes. Each of the source and drain contact electrodes can be electrically shorted to an underlying embedded electrode to reduce parasitic capacitance.
First claim
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What is claimed is: 1. A structure comprising: a first embedded electrode and a second embedded electrode located in an insulator layer of a substrate; a dielectric layer located directly on a topmost surface of said insulator layer; a buried gate electrode embedded in said insulator layer and having a topmost surface in direct contact with a bottom surface of said dielectric layer; and a plurality of carbon nanotubes that are substantially parallel to one another and locate…
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- What does patent US8987705B2 cover?
- Carbon nanotubes can be aligned with compatibility with semiconductor manufacturing processes, with scalability for forming smaller devices, and without performance degradation related to structural damages. A planar structure including a buried gate electrode and two embedded electrodes are formed. After forming a gate dielectric, carbon nanotubes are assembled in a solution on a surface of th…
- Who is the assignee on this patent?
- IBM, Karlsruher Inst Technologie, Karlsruher Inst Technologie
- What technology area does this patent fall under?
- Primary CPC classification H10K71/12. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 24 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).