Manufacturing method for a porous microneedle array and corresponding porous microneedle array and corresponding substrate composite

Patent metadata

Field	Value
Publication number	US-8986256-B2
Application number	US-92580410-A
Country	US
Kind code	B2
Filing date	Oct 29, 2010
Priority date	Nov 10, 2009
Publication date	Mar 24, 2015
Grant date	Mar 24, 2015

Abstract

A manufacturing method for a porous microneedle array includes: forming a plurality of porous microneedle arrays, each having at least one microneedle and a porous carrier zone lying beneath it on the face of a semiconductor substrate; forming an interlayer between a non-porous residual layer of the semiconductor substrate located on the back side of the semiconductor substrate and the carrier zone, which has greater porosity than the carrier zone; detaching the residual layer from the carrier zone by breaking up the interlayer; and separating the microneedle arrays into corresponding chips.

First claim

What is claimed is:

1. A porous microneedle array, comprising:
a porous carrier zone formed at a face of a semiconductor substrate;
plurality of microneedles disposed on a portion of the porous carrier zone between edge structures disposed on the face of the semiconductor substrate, wherein the edge structures vertically rise to above the plurality of microneedles; and
a plastic cap positioned over the plurality of microneedles and covering the plurality of microneedles, wherein the plastic cap includes a surface extending continuously in a plane between flanges that interact with the edge structures for positioning the surface over the plurality of microneedles.

2. The porous microneedle array of claim 1 , wherein the surface is a single planar surface that extends from a first of the flanges to a second of flanges.

3. The porous microneedle array of claim 2 , wherein the surface is one of a plurality of surfaces which the plastic cap includes, each of the surfaces forming a single plane that extends from a respective first one of the flanges to a respective second one of the flanges and each of planar surfaces extending over a respective plurality of the microneedles.

4. A substrate composite, comprising:
a plurality of porous microneedle arrays formed on a front face of a semiconductor substrate, each microneedle array including:
a porous carrier zone; and
a plurality of microneedles above a portion of the porous carrier zone and between edge structures that vertically rise from the carrier zone to above the plurality of microneedles; and
a plastic cap substrate positioned over the microneedle arrays, wherein the plastic cap substrate includes a plurality of surfaces that each extends continuously in a single plane and that are separated from each other by flanges that interact with the edge structures for positioning respective ones of the surfaces over respective ones of the plurality of porous microneedle arrays, each of the arrays including more than one microneedle.

5. The substrate composite as recited in claim 4 , wherein each microneedle array is laterally delimited by a respective pair of the vertically-rising edge structures.

6. The substrate composite as recited in claim 4 , further comprising:
an inter layer provided between the porous carrier zone and a non-porous residual layer of the semiconductor substrate located below the porous carrier zone, wherein the interlayer has greater porosity than the carrier zone.

7. The substrate composite as recited in claim 6 , wherein the semiconductor substrate is a wafer substrate.

8. The substrate composition as recited in claim 4 , wherein flanges of each of a plurality of pairs of a subset of the flanges are separated from each other by a respective recess into which a respective one of the edge structures is form-fittingly positioned.

9. The substrate composite as recited in claim 4 , wherein each of the surfaces extends from a first respective one of the flanges to a second respective one of the flanges.

10. A porous microneedle array, comprising:
a porous carrier zone formed at a face of a semiconductor substrate;
plurality of microneedles disposed on a portion of the porous carrier zone between edge structures disposed on the face of the semiconductor substrate; and
a plastic cap positioned over the plurality of microneedles and covering the plurality of microneedles;
wherein:
the edge structures vertically rise to above the plurality of microneedles;
the plastic cap includes a substantially planar surface extending between flanges that interact with the edge structures for positioning the substantially planar surface over the plurality of microneedles; and
an open space separates between the substantially planar surface and the plurality of microneedles over which the substantially planar surface is positioned.

Assignees

• Scholten Dick
• Stumber Michael
• Laermer Franz
• Feyh Ando
• Bosch Gmbh Robert

Inventors

• Scholten Dick
• Stumber Michael
• Laermer Franz
• Feyh Ando

Classifications

• Y10T225/10

  Methods · CPC title

• Y10T225/12

  With preliminary weakening · CPC title

• B81B2201/055

  Microneedles · CPC title

• B81C2201/0114

  Electrochemical etching, anodic oxidation · CPC title

• B81C2203/054

  using structural alignment aids, e.g. spacers, interposers, male/female parts, rods or balls · CPC title