Base, IC, and coupling interposer with boundary scan register

US8984359B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8984359-B2
Application numberUS-201314023041-A
CountryUS
Kind codeB2
Filing dateSep 10, 2013
Priority dateFeb 7, 2011
Publication dateMar 17, 2015
Grant dateMar 17, 2015

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Abstract

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The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.

First claim

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What is claimed is: 1. A device comprising: A. a base substrate having functional input outputs, functional output inputs, a test data in output, a test mode select output, a test clock output, and a test data out input; B. an integrated circuit die having functional inputs and functional outputs, and having no connection to any of the test data in output, the test mode select output, the test clock output, and the test data out input; and C. an interposer, including: i. firs…

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What does patent US8984359B2 cover?
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also include…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification G01R31/318536. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).