Method, apparatus, and system for energy efficiency and energy conservation including dynamic C0-state cache resizing

Patent metadata

Field	Value
Publication number	US-8984311-B2
Application number	US-201113341657-A
Country	US
Kind code	B2
Filing date	Dec 30, 2011
Priority date	Dec 30, 2011
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

Embodiments of systems, apparatuses, and methods for energy-efficient operation of a device are described. In some embodiments, a cache performance indicator of a cache is monitored, and a set of one or more cache performance parameters based on the cache performance indicator is determined. The cache is dynamically resized to an optimal cache size based on a comparison of the cache performance parameters to their energy-efficient targets to reduce power consumption.

First claim

What is claimed is:

1. A method comprising:
monitoring a cache performance indicator of a cache;
determining a set of one or more cache performance parameters based on the cache performance indicator;
comparing the set of one or more cache performance parameters to a set of one or more energy-efficient targets for those cache performance parameters;
dynamically resizing the cache to an optimal cache size based on the comparison of the cache performance parameters to the energy-efficient targets to reduce power consumption;
entering a deep-sleep state by shrinking the cache; and
waking up from the deep-sleep state by expanding the cache to a size that was determined to be the optimal cache size prior to entering the deep-sleep state.

2. The method of claim 1 , wherein the cache performance indicator of the cache is a cache miss counter, and the set of one or more cache performance parameters includes at least one of a cache miss per cycle measurement, a target cache miss per cycle deviation, and a cache miss per cycle variation.

3. The method of claim 2 , wherein the set of one or more energy-efficient targets includes a target cache miss per cycle; and
dynamically resizing the cache includes resizing the cache to tune the cache miss per cycle measurement toward the target cache miss per cycle.

4. The method of claim 2 , wherein the set of one or more energy-efficient targets includes a convergence threshold; and
dynamically resizing the cache includes resizing the cache until the target cache miss per cycle deviation is less than the convergence threshold.

5. The method of claim 2 , wherein the set of one or more energy-efficient targets includes a stability threshold; and
dynamically resizing the cache includes reverting the cache to a full cache size when a workload phase change is detected, wherein the workload phase change is detected when the cache miss per cycle variation is above the stability threshold.

6. The method of claim 1 , wherein the cache is expanded by enabling one or more cache ways of the cache, and the cache is shrunk by disabling one or more cache ways of the cache.

7. The method of claim 1 , wherein the cache is a last level cache (LLC).

8. A non-transitory, machine readable storage medium containing instructions that when processed by a machine causes the machine to fabricate logic capable of performing a method, the method comprising:
monitoring a cache performance indicator of a cache;
determining a set of one or more cache performance parameters based on the cache performance indicator;
comparing the set of one or more cache performance parameters to a set of one or more energy-efficient targets for those cache performance parameters;
dynamically resizing the cache to an optimal cache based on the comparison of the cache performance parameters to the energy-efficient targets to reduce power consumption;
entering a deep-sleep state by shrinking the cache; and
waking up from the deep-sleep state by expanding the cache to a size that was determined to be the optimal cache size prior to entering the deep-sleep state.

9. The non-transitory, machine readable storage medium of claim 8 , wherein the cache performance indicator of the cache is a cache miss counter, and the set of one or more cache performance parameters includes at least one of a cache miss per cycle measurement, a target cache miss per cycle deviation, and a cache miss per cycle variation.

10. The non-transitory, machine readable storage medium of claim 9 , wherein the set of one or more energy-efficient targets includes a target cache miss per cycle; and
dynamically resizing the cache includes resizing the cache to tune the cache miss per cycle measurement towards the target cache miss per cycle.

11. The non-transitory, machine readable storage medium of claim 9 , wherein the set of one or more energy-efficient targets includes a convergence threshold; and
dynamically resizing the cache includes resizing the cache until the target cache miss per cycle deviation is less than the convergence threshold.

12. The non-transitory, machine readable storage medium of claim 9 , wherein the set of one or more energy-efficient targets includes a stability threshold; and
dynamically resizing the cache includes reverting the cache to full size when a workload phase change is detected, wherein the workload phase change is detected when the cache miss per cycle variation is above the stability threshold.

13. The non-transitory, machine readable storage medium of claim 8 , wherein the cache is expanded by enabling one or more cache ways of the cache, and the cache is shrunk by disabling one or more cache ways of the cache.

14. The non-transitory, machine readable storage medium of claim 8 , wherein the cache is a last level cache (LLC).

15. An apparatus for efficient energy consumption comprising:
a cache including a plurality of cache partitions;
at least one central processing unit (CPU) core coupled to the cache; and
a power control unit (PCU) adapted to determine an optimal cache size of the cache based on monitoring a cache performance indicator of the cache, and to reduce power consumption by selectively powering one or more cache partitions to dynamically resize the cache to achieve the optimal cache size, wherein the PCU is to enable a deep-sleep state by shrinking the cache, and to wake up from the deep-sleep state by expanding the cache to a size that was determined to be the optimal cache size prior to entering the deep-sleep state.

16. The apparatus of claim 15 , wherein the cache performance indicator of the cache is a cache miss counter.

17. The apparatus of claim 15 , wherein the cache is a last level cache (LLC), and each of the cache partitions is a cache way of the cache.

18. A non-transitory, machine readable storage medium containing instructions that when processed by a machine to cause the machine to fabricate logic comprising:
a power control unit (PCU) adapted to determine an optimal cache size of a cache based on monitoring a cache performance indicator of the cache, and to reduce power consumption by selectively powering one or more cache partitions to dynamically resize the cache to achieve the optimal cache size, wherein the PCU is to enable a deep-sleep state by shrinking the cache, and to wake up from the deep-sleep state by expanding the cache to a size that was determined to be the optimal cache size prior to entering the deep-sleep state.

Assignees

• Moses Jaideep
• Illikkal Rameshkumar G
• Iyer Ravishankar
• Bendt Jared E
• Srinivasan Sadagopan
• Herdrich Andrew J
• Choubal Ashish V
• Ananthakrishnan Avinash N
• Degalahal Vijay S R
• Intel Corp

Inventors

• Moses Jaideep
• Illikkal Rameshkumar G
• Iyer Ravishankar
• Bendt Jared E
• Srinivasan Sadagopan
• Herdrich Andrew J
• Choubal Ashish V
• Ananthakrishnan Avinash N
• Degalahal Vijay S R

Classifications

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• G06F1/3225

  of memory devices · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title

• G06F1/3275 Primary

  Power saving in memory, e.g. RAM, cache · CPC title