Reducing network latency during low power operation

Patent metadata

Field	Value
Publication number	US-8984309-B2
Application number	US-31354808-A
Country	US
Kind code	B2
Filing date	Nov 21, 2008
Priority date	Nov 21, 2008
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A method comprising:
powering down a first group of cores of a multicore processor responsive to determining that a traffic rate of incoming packets to the multicore processor is less than a threshold;
receiving an incoming packet in a packet buffer and associating the incoming packet with a flow identifier;
based on the flow identifier, determining a core of the multicore processor to which the incoming packet is to be directed; and
if the core is in the first group of cores, transmitting a power management hint to cause the core to be powered up after being powered down and sending the incoming packet to the core when the incoming packet reaches a head of the packet buffer, wherein the core is powered up when the incoming packet initially reaches the head of the packet buffer.

2. The method of claim 1 , further comprising transmitting a second power management hint to cause at least one other core to be powered down.

3. The method of claim 1 , wherein determining the core of the multicore processor to which the incoming packet is to be directed comprises accessing a mapping table that stores entries, wherein each entry includes a corresponding flow identifier and a corresponding core identifier.

4. The method of claim 3 , further comprising accessing the mapping table using a content addressable memory.

5. The method of claim 1 , further comprising transmitting a second power management hint to a second component associated with the core to cause the second component to be powered up if the core is in the first group of cores.

6. The method of claim 5 , further comprising transmitting the second power management hint to a bus logic coupled to the powered up core to cause the bus logic to be powered up.

7. The method of claim 1 , wherein the core is to handle the incoming packet without introducing latency associated with power-up of the core when handling the incoming packet.

8. An article comprising a non-transitory machine-accessible storage medium including instructions that when executed cause a system to:
compare a level of traffic received at a peripheral input/output (I/O) interface to a traffic threshold and based on the comparison, send a power management hint from the peripheral I/O interface to cause at least one core of a processor to be placed into a low power state; and
responsive to a packet received at the peripheral I/O interface and directed to the at least one core, send a second power management hint to cause the at least one core to be placed from the low power state to an active state and send the packet to the at least one core when the packet reaches a head of a packet buffer, wherein the at least one core is powered up when the packet initially reaches the head of the packet buffer.

9. The article of claim 8 , further comprising instructions that when executed enable the system to send the power management hint to an operating system (OS) scheduler to cause a plurality of cores of the processor to be placed into the active state responsive to the level of traffic being greater than a first threshold level and less than a second threshold level.

10. The article of claim 8 , further comprising instructions that when executed enable the system to associate the incoming packet with a flow identifier, and based on the flow identifier, determine that the packet is to be directed to the at least one core.

11. An apparatus comprising:
a packet buffer to store packets received from a network, the packet buffer including a plurality of buffers each to store a corresponding packet and a corresponding flow identifier; and
logic to:
match a first stored packet in the packet buffer with a target core to which the first stored packet is to be sent based on the corresponding flow identifier, send a power management hint to cause the target core to be powered up after being in a low power state, and send the first stored packet to the target core when the first stored packet reaches a head of the packet buffer, wherein the target core is powered up when the first stored packet initially reaches the head of the packet buffer.

12. The apparatus of claim 11 , wherein the logic is further to transmit a second power management hint to cause at least one other core to be powered down.

13. The apparatus of claim 11 , wherein the apparatus comprises a network interface controller (NIC).

14. The apparatus of claim 13 , wherein the NIC is to send the power management hint to an operating system (OS) scheduler.

15. The apparatus of claim 13 , wherein the NIC is to send the power management hint to the target core.

16. The apparatus of claim 11 , wherein the logic is further to determine a level of network traffic received from the network, compare the level to a traffic threshold and determine a comparison result, and based on the comparison result, determine whether to send another power management hint to cause another target core of a multicore processor to be placed into the low power state.

Assignees

• Memon Mazhar I
• Larsen Steen K
• Veal Bryan E
• Lake Daniel S
• Schluessler Travis T
• Intel Corp

Inventors

• Memon Mazhar I
• Larsen Steen K
• Veal Bryan E
• Lake Daniel S
• Schluessler Travis T

Classifications

• H04L49/90 Primary

  Buffering arrangements · CPC title

• G06F1/3209 Primary

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title

• H04L12/12

  Arrangements for remote connection or disconnection of substations or of equipment thereof · CPC title

• Y02B60/34

  Cross-Sectional Technologies · mapped topic

• Y02B30/70

  Efficient control or regulation technologies, e.g. for control of refrigerant flow, motor or heating · CPC title