Vector checksum instruction
US-9471311-B2 · Oct 18, 2016 · US
US8984039B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8984039-B2 |
| Application number | US-201213367032-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 6, 2012 |
| Priority date | Feb 6, 2012 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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A residue generating circuit for an execution unit that supports vector operations includes an operand register and a residue generator coupled to the operand register. The residue generator includes a first residue generation tree coupled to a first section of the operand register and a second residue generation tree coupled to a second section of the operand register. The first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register. The second residue generation tree is configured to generate a second residue for second data included in a second section of the operand register. The first section of the operand register includes a different number of register bits than the second section of the operand register.
Opening claim text (preview).
What is claimed is: 1. A residue generating circuit for an execution unit that supports vector operations, comprising: an operand register; and a residue generator coupled to the operand register, the residue generator including: a first residue generation tree coupled to a first section of the operand register, wherein the first residue generation tree is configured to generate a first residue for first data included in the first section of the operand register; and a second…
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