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US-2024431161-A1 · Dec 26, 2024 · US
US8982015B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8982015-B2 |
| Application number | US-73614409-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 31, 2009 |
| Priority date | Apr 22, 2008 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Official abstract text for this publication.
A shift register includes cascade-connected stages, each of which includes a data latch and an output stage. In at least one embodiment, the latch has a single data input which, in use, receives a date signal from a preceding or succeeding stage. The output stage includes a first switch, which passes a clock signal to the stage output when the output stage is activated by the latch. The output stage also comprises a second switch, which passes the lower supply voltage to the stage output when the output stage is inactive.
Opening claim text (preview).
The invention claimed is: 1. A shift register comprising: a plurality of stages, each of at least some of the stages including a data latch and an output stage, each data latch including a single data input arranged, when the shift register is in use, to receive a data signal from a single adjacent one of the stages, and each output stage including a first switch arranged to pass a clock signal to a stage output when the output stage is active and a second switch arranged to…
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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