Packaged power semiconductor with interconnection of dies and metal clips on lead frame

Patent metadata

Field	Value
Publication number	US-8981539-B2
Application number	US-201313913717-A
Country	US
Kind code	B2
Filing date	Jun 10, 2013
Priority date	Jun 10, 2013
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

First claim

The invention claimed is:

1. A power semiconductor device comprising:
a lead frame unit, a control die, a first die and a second die, a first metal clip and a second metal clip;
wherein the lead frame unit comprises a die paddle, a first pin, a second pin, a first row of carrier pins and a second row of carrier pins, adjacent to the die paddle;
the die paddle comprises a first transverse edge and a second transverse edge opposite to the first transverse edge, a first longitudinal edge and a second longitudinal edge opposite to the first longitudinal edge, wherein the first pin comprises a bonding area adjacent to and extending along the first transverse edge of the die paddle, and the second pin comprising a bonding area adjacent to and extending along the second transverse edge of the die paddle;
both of the first row of carrier pins and the second row of carrier pins are positioned at one side of the second longitudinal edge of the die paddle away from the first longitudinal edge, each carrier pin of the first row of carrier pins is substantially parallel to each other and extends from an extension line of the first pin towards a center line between the first transverse edge and the second transverse edge, and each carrier pin of the second row of carrier pins is substantially parallel to the second longitudinal edge and extends from the second pin towards the center line;
each of the first die and the second die has a back surface attached onto the die paddle and the control die is attached onto the first row of carrier pins and the second row of carrier pins, wherein the first metal clip electrically connects a first electrode at a front surface opposite to the back surface of the first die to the first pin and the second metal clip electrically connects a first electrode at a front surface opposite to the back surface of the second die to the second pin.

2. The power semiconductor device of claim 1 , wherein the die paddle comprises a connecting part connecting the die paddle at the second longitudinal edge to an innermost carrier pin of the first row of carrier pins close to the die paddle.

3. The power semiconductor device of claim 2 , wherein a third electrode at the back surface of the first die and a third electrode at the back surface the second die are directly attached on the top surface of the die paddle.

4. The power semiconductor device of claim 3 , wherein each carrier pin of the first row of carrier pins and the second row of carrier pins comprises an upper pin and a lower pin connected together, wherein top surfaces of the upper pins of all carrier pins are substantially coplanar with the front surfaces of the first die and the second die;
wherein the control die is flipped and attached on the first row of carrier pins and the second row of carrier pins and partially overlaps the first die and the second die so that a plurality of metal bumps formed on a plurality of electrode pads at a front surface of the control die are respectively aligned with and electrically connected with a second electrode at the front surface of the first die and a second electrode at the front surface of the second die;
the metal bumps formed on other electrode pads at the front surface of the control die are respectively aligned with and electrically connected with corresponding upper pins of the carrier pins of the first row of carrier pins and the second row of carrier pins.

5. The power semiconductor device of claim 4 further comprising a plastic package body for covering the lead frame unit, the first die, the second die, the control die, the first metal clip, the second metal clip and the metal bumps, with bottom surfaces of the lower pins, a bottom surface of the die paddle, and bottom surfaces of the first pin and the second pin exposed from a bottom surface of the plastic package body.

6. The power semiconductor device of claim 2 , wherein the die paddle comprises a recessed area at the top surface and the first die and the second die are positioned in the recessed area; thus, the third electrodes at the back surface of the first die and the second die are attached on the recessed area; and top surfaces of the carrier pins of the first row of carrier pins and the second row of carrier pins are substantially coplanar with the respective front surfaces of the first die and the second die.

7. The power semiconductor device of claim 6 , wherein the control die is flipped and attached on the first row of carrier pins and the second row of carrier pins and partially overlaps the first die and the second die so that a plurality of metal bumps formed on a plurality of electrode pads at the front surface of the control die are respectively aligned with and electrically connected with a second electrode at the front surface of the first die and a second electrode at the front surface of the second die;
the metal bumps formed on other electrode pads at the front surface of the control die are respectively aligned with and electrically connected with the corresponding carrier pins of the first row of carrier pins and the second row of carrier pins.

8. The power semiconductor device of claim 7 further comprising a plastic package body for covering the lead frame unit, the first die, the second die, the control die, the first metal clip and the second metal clip and the metal bumps, with bottom surfaces of the carrier pins, a bottom surface of the die paddle, and bottom surfaces of the first pin and the second pin exposed from a bottom surface of the plastic package body.

9. The power semiconductor device of claim 7 , wherein each of the first metal clip and the second metal clip comprises a first part and a second part connected to the first part with the first part and the second part positioned in planes with differences in height, bottom surfaces of the first parts of the first metal clip and the second metal clip are respectively mounted on the first electrodes of the first die and the second die, and the second parts of the first metal clip and the second metal clip are respectively mounted on bonding areas of the first pin and the second pin .

10. The power semiconductor device of claim 9 further comprising a plastic package body for covering the lead frame unit, the first die, the second die, the control die, the first metal clip, the second metal clip and the metal bumps;
a back surface of the control die is coplanar with top surfaces of the respective first parts of the first metal clip and the second metal clip, wherein bottom surfaces of the carrier pins, a bottom surface of the die paddle, and bottom surfaces of the first pin and the second pin are exposed from a bottom surface of the plastic package body, and the top surface of the respective first parts of the first metal clip and the second metal clip and the back surface of the control die are exposed from a top surface of the plastic package body.

11. The power semiconductor device of claim 1 , wherein third electrodes at the back surfaces of the first die and the second die are attached on the top surface of the die pad and the control die is flipped and attached on the first row of carrier pins and the second row of carrier pins, and metal bumps formed on respective electrode pads at a front surface of the control die thereof are respectively aligned with and electrically connected with the corresponding carrier pins.

12. The power semiconductor device of claim 11 , wherein a length of the first pin extending along the first transverse edge is less than a length of the first transverse edge, and a length of the second pin extending along the second transverse edge is less than a length of the second transverse edge;
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Assignees

• Xue Yan Xun
• Yilmaz Hamza
• Alpha & Omega Semiconductor

Inventors

• Xue Yan Xun
• Yilmaz Hamza

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/763

  between laterally-adjacent chips · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title