Silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-8981385-B2
Application number	US-201314104975-A
Country	US
Kind code	B2
Filing date	Dec 12, 2013
Priority date	Jan 16, 2013
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

A silicon carbide semiconductor device includes a silicon carbide substrate. The silicon carbide substrate is composed of an element region provided with a semiconductor element portion and a termination region surrounding the element region as viewed in a plan view. The semiconductor element portion includes a drift region having a first conductivity type. The termination region includes a first electric field relaxing region contacting the element region and having a second conductivity type different from the first conductivity type, and a second electric field relaxing region arranged outside the first electric field relaxing region as viewed in the plan view, having the second conductivity type, and spaced from the first electric field relaxing region. A ratio calculated by dividing a width of the first electric field relaxing region by a thickness of the drift region is not less than 0.5 and not more than 1.83.

First claim

What is claimed is:

1. A silicon carbide semiconductor device, comprising a silicon carbide substrate composed of an element region provided with a semiconductor element portion and a termination region surrounding said element region as viewed in a plan view,
said semiconductor element portion including a drift region having a first conductivity type,
said termination region including
a first electric field relaxing region contacting said element region and having a second conductivity type different from said first conductivity type, and
a second electric field relaxing region arranged outside said first electric field relaxing region as viewed in said plan view, having said second conductivity type, and spaced from said first electric field relaxing region,

a ratio calculated by dividing a width of said first electric field relaxing region by a thickness of said drift region being not less than 0.5 and not more than 1.83,
wherein said second electric field relaxing region includes a plurality of guard ring portions, and
wherein, in a case where any two guard ring portions are selected from among said plurality of guard ring portions, the guard ring portion arranged on an outer peripheral side as viewed in the plan view has a width which is not more than that of the guard ring portion arranged on an inner peripheral side, and the guard ring portion arranged on an outermost peripheral side has a width which is smaller than that of the guard ring portion arranged on an innermost peripheral side.

2. The silicon carbide semiconductor device according to claim 1 , wherein each of said plurality of guard ring portions has a width smaller than the width of said first electric field relaxing region.

3. The silicon carbide semiconductor device according to claim 1 , wherein the number of said plurality of guard ring portions is not less than 6 and not more than 15.

4. The silicon carbide semiconductor device according to claim 3 , wherein the number of said plurality of guard ring portions is not less than 12 and not more than 15.

5. The silicon carbide semiconductor device according to claim 1 , wherein said silicon carbide semiconductor device is any of a MOSFET, an IGBT, a schottky barrier diode, and a P/N diode.

Assignees

• Sumitomo Electric Industries

Inventors

• Wada Keiji
• Masuda Takeyoshi
• Hiyoshi Toru

Classifications

• H10D12/032

  of vertical IGBTs · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D8/051 Primary

  of Schottky diodes · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title