Methods of forming semiconductor devices
US-2024387699-A1 · Nov 21, 2024 · US
Methods for device fabrication using pitch reduction
US8980756B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980756-B2 |
| Application number | US-83044907-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 30, 2007 |
| Priority date | Jul 30, 2007 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Abstract
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Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers may be formed by pitch multiplication. Other methods for device fabrication are provided.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for device fabrication, comprising: forming a first mask over a semiconductor substrate; photolithographically forming a first pattern of features over the first mask, the features of the first pattern of features having a first width; forming a second pattern of features over the first mask using spacers formed by pitch multiplication subsequent to photolithographically forming the first pattern or features, features of the second pattern of fe…
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Classifications
Electricity · mapped topic
- H10P76/4085Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8980756B2 cover?
- Embodiments of a method for device fabrication by reverse pitch reduction flow include forming a first pattern of features above a substrate and forming a second pattern of pitch-multiplied spacers subsequent to forming the first pattern of features. In embodiments of the invention the first pattern of features may be formed by photolithography and the second pattern of pitch-multiplied spacers…
- Who is the assignee on this patent?
- Tran Luan C, Giridhar Raghupathy, Micron Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification H10P76/4085. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).