All-tungsten scheme for source/drain contact, source/drain via, and gate via
US-2024395618-A1 · Nov 28, 2024 · US
US8980740B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980740-B2 |
| Application number | US-201313786627-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 6, 2013 |
| Priority date | Mar 6, 2013 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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A process of modulating the thickness of a barrier layer deposited on the sidewalls and floor of a recessed feature in a semiconductor substrate is disclosed. The process includes altering the surface of the conductive feature on which the barrier layer is deposited by annealing in a reducing atmosphere and optionally additionally, silylating the dielectric surface that forms the sidewalls of the recessed feature.
Opening claim text (preview).
What is claimed is: 1. A process comprising: providing a substrate having both an exposed dielectric surface and an exposed metal surface; exposing both said metal surface to a reducing agent and said dielectric surface to a reactive silane; and depositing a barrier layer over said exposed metal surface and said exposed dielectric surface; wherein the thickness of said barrier layer is the same or greater over said metal surface than over said dielectric surface.…
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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