Semiconductor devices and methods of manufacturing
US-12166025-B2 · Dec 10, 2024 · US
Solder collapse free bumping process of semiconductor device
US8980739B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980739-B2 |
| Application number | US-201213473728-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 17, 2012 |
| Priority date | May 18, 2011 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exposed by the photoresist pattern; forming a solder layer by performing a secondary electroplating on the pillars; removing the photoresist pattern; forming solder bumps, in which solders partially cover surfaces of the pillars, by performing a reflow process on the semiconductor substrate; and removing portions of the seed layer formed in regions other than the solder bumps.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming bumps of a semiconductor device with reduced solder bump collapse, the method comprising: preparing a semiconductor substrate in which pads are exposed externally through a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose a portion of the seed layer on the pads; forming pillars by performing a primary electroplating at a region exposed by the photoresist pattern; formi…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8980739B2 cover?
- A method of forming bumps of a semiconductor device with reduced solder bump collapse. The method includes preparing a semiconductor substrate in which pads are exposed externally from a passivation layer; forming a seed layer on the semiconductor substrate; forming a photoresist pattern to expose the seed layer on the pads; forming pillars by performing a primary electroplating on a region exp…
- Who is the assignee on this patent?
- Cho Moon-Gi, Lee Sang-Hee, Park Jeong-Woo, and 1 more
- What technology area does this patent fall under?
- Primary CPC classification H10W72/20. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).