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Ultra-high voltage N-type-metal-oxide-semiconductor (UHV NMOS) device and methods of manufacturing the same
US8980717B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8980717-B2 |
| Application number | US-201314071768-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 5, 2013 |
| Priority date | Mar 24, 2011 |
| Publication date | Mar 17, 2015 |
| Grant date | Mar 17, 2015 |
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Abstract
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An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW comprising a source and a bulk; a gate extended from the source and bulk PW to a portion of the first HVNW region, and a drain disposed within another portion of the first HVNW region that is opposite to the gate; a P-Top layer disposed within the first HVNW region, the P-Top layer positioned between the drain and the source and bulk PW; and an n-type implant layer formed on the P-Top layer.
First claim
Opening claim text (preview).
What is claimed is: 1. A method for manufacturing ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device, at least comprising: providing a substrate of P-type material; forming a first high-voltage N-well (HVNW) region in a portion of the substrate; forming a second HVNW region in another portion of the substrate, wherein the second HVNW region is disposed at a high-side operation region of the substrate; forming at least two p-wells (PWs) separately in a regi…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US8980717B2 cover?
- An ultra-high voltage n-type-metal-oxide-semiconductor (UHV NMOS) device with improved performance and methods of manufacturing the same are provided. The UHV NMOS includes a substrate of P-type material; a first high-voltage N-well (HVNW) region disposed in a portion of the substrate; a source and bulk p-well (PW) adjacent to one side of the first HVNW region, and the source and bulk PW compri…
- Who is the assignee on this patent?
- Macronix Int Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D62/111. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 17 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).