Method for fabricating a metal high-k gate stack for a buried recessed access device

Patent metadata

Field	Value
Publication number	US-8980713-B2
Application number	US-201313907001-A
Country	US
Kind code	B2
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	Mar 17, 2015
Grant date	Mar 17, 2015

Abstract

A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain.

First claim

What is claimed is:

1. A method for fabricating a gate for a buried recess access device comprising:
depositing a first oxide layer on a substrate;
depositing a polysilicon layer on the first oxide layer;
masking the polysilicon layer with a pattern to produce an initial set of trenches;
etching a plurality of gate trenches in the substrate;
depositing a dummy gate in each of the plurality of gate trenches;
filling the plurality of gate trenches with a second oxide layer;
removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches;
depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches;
depositing a third oxide layer on the metal gate;
forming a contact a source/drain regions; and
implanting and activating the source/drain regions prior to forming a gate stack comprising a metal electrode and high-k dielectric using a dummy gate stack as a mask for source/drain implantation.

2. The method of claim 1 further comprising, after the plurality of trenches is etched:
depositing a fourth oxide layer in each of the plurality of trenches, prior to depositing the dummy gate in each of the plurality of trenches.

3. The method of claim 1 wherein an etching process is used to etch the plurality of gate trenches, the etching process being one of a dry etch or wet etch process.

4. The method of claim 1 further comprising:
etching the polysilicon layer leaving the first oxide remaining above each source drain region; and
performing silicidation on the source/drain region to form a plurality of dummy gate electrodes.

5. The method of claim 4 further comprising:
depositing a silicon nitride layer on each of the plurality of dummy gate electrodes.

6. The method of claim 5 further comprising:
polishing the silicon nitride using a chemical mechanical planarization (CMP) process.

7. The method of claim 2 further comprising:
forming the dummy gate out of polysilicon; and
forming all oxide layers using silicon oxide (SiO2).

8. The method of claim 1 wherein the metal gate is composed of one of titanium nitride, Ti, TiAlNi, TiSi, Ni, NiSi, Hf, HfSi, W, Ta, TaSi, Co, CoSi, Ru, AlN.

9. The method of claim 1 wherein the high-K dielectric is comprised of one of HfO2, HfOIO2, HfSiO, Ta2O5, Al2O3, ZrO2.

10. A method for fabricating a gate for a buried recess access device comprising:
forming, a plurality of active areas on a first oxide layer deposited on a silicon substrate by:
depositing the first oxide layer on the silicon substrate;
depositing a polysilicon layer on the first oxide layer; and
masking the polysilicon layer to form an initial set of trenches;

implanting and activating source/drain regions prior to forming a gate stack comprising a metal electrode and high-k dielectric using a dummy gate stack as a mask for source/drain implantation;
etching a plurality of gate trenches in the silicon substrate between each of the active areas;
depositing a high-k dielectric layer on sides and a bottom of the plurality of gate trenches;
depositing a metal gate on the high-k dielectric in each of the plurality of gate trenches; and
forming a contact on the source drain regions in each of the plurality of gate trenches.

11. The method of claim 10 further comprising:
depositing a second oxide layer in the initial set of trenches;
after implanting and activating the source/drain region in the silicon substrate, etching the polysilicon layer using an etch selective to polysilicon leaving a remaining portion of the first oxide layer; and
performing silicidation on the source/drain region to form a silicide layer.

12. The method of claim 11 further comprising:
depositing a silicon nitride layer on the silicide; and
polishing the silicon nitride on the silicide layer.

13. The method of claim 12 wherein the polishing is performed via a chemical mechanical planarization (CMP) process.

14. The method of claim 10 wherein the high K dielectric is composed of one of HfO2, HfOIO2, HfSiO, Ta2O5, Al2O3, ZrO2.

15. The method of claim 10 wherein the metal gate is composed of one of titanium nitride, Ti, TiAlNi, TiSi, Ni, NiSi, Hf, HfSi, W, Ta, TaSi, Co, CoSi, Ru, AlN.

Assignees

• Sony Corp

Inventors

• Mayuzumi Satoru
• Fischer Mark
• Violette Michael

Classifications

• H10P30/20

  into semiconductor materials, e.g. for doping · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title